Senior RTL Design Engineer, California

Senior RTL Design Engineer

Remote / work from home

US Citizen or US Permanent Resident

Full-time/employee + Benefits + 401k + Stock Options

Job Responsibilities:

Participate in architectural feasibility studies

Develop micro-architecture specifications based on the SoC requirements

Design, implement and integrate complex SoC blocks

Develop block-level test cases to deliver fully functional designs

Develop synthesis constraints and resolve timing issues

Resolve Lint, CDC, and DFT related issues

Identify and resolve RTL and GLS failures at block and chip level

Participate in ECO implementation

Assist with silicon bring-up

Skills & Experience:

BSEE/MSEE with 10+ years of SoC design/architecture experience

RTL Design including HVLs and HDLs (SystemVerilog, Verilog)

Third Party IP Integration experience

Logic synthesis and static timing analysis

SoC design flow including chip-level design, block/IP design and behavioral modeling

Modeling SoC architectures with FPGAs

Working knowledge of standard bus protocols such as AXI/AMBA/TileLink

Experience with RISC-V architecture

Working knowledge of PCIe and DDR

Clock domain crossing methodologies

Scripting languages such as Python, Perl, Tcl, shell, etc.

Strong familiarity with EDA tools

Strong problem solving and debugging capabilities

Working knowledge of SoC design with CHISEL is a plus

Asynchronous logic design is a plus