CPU Implementation Silicon Correlation Engineer, Santa Clara

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there"s no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want join us in these pursuits? Join us to help deliver the next groundbreaking Apple product!\\n\\nAs we continue to push CPU performance and efficiency in the most advanced technology nodes validating and correlating our physical design point to silicon is of utmost importance. We want to ensure that the frequencies, voltages, and power we target in pre-silicon design are realizable on silicon and in the final products we ship to our customers. In this role as a CPU Implementation Silicon Correlation Engineer, you will be performing data analysis using pre-silicon and post-silicon data to establish silicon correlation to design targets. In this role as a CPU Implementation Silicon Correlation Engineer, you will be working on the following:\\n\\n• Obtain process-related silicon measurement data from product and technology team\\n• Analyze pre-silicon timing runs to comprehend margins and relate it to measured silicon parameters\\n• Work with post-silicon teams in evaluating ROI of design and methodology features\\n•Analyze post-silicon speed debug data to help identify and root cause failing paths Minimum BS and 10 years of relevant industry experience\\nExperience with a chip tapeout of a custom or PnR block\\nExperience with STA\\nExperience running spice simulations and analysis\\nExperience with data parsing, analysis, andrepresentation/plotting skills Chip design experience including experience in CPU design\\nGood understanding of std cell architecture and design\\nWorking knowledge of device technology and spice models\\nFamiliarity with ATPG pattern framework\\nAwareness of PNR tool flows\\nLanguage proficiencyin TCL, Perl, and Python\\nAbility to work with cross-functional teams spanning pre-silicon design, technology and post-silicon debug